Plating Method
DIG
Direct immersion gold is an abbreviation for direct method of substitution gold plating on copper. Since Ni plating is omitted, it is possible to handle fine pitch compared to ENIG. The layer composition is Cu-Au.
ENIG
A method of electroless nickel plating and auto catalytic gold plating on copper, an abbreviation for electroless nickel immersion gold. The layer composition is Cu-Ni-Au.
EPIG
Electroless palladium plating and auto catalytic gold plating on copper, abbreviation for Electroless Palladium Immersion Gold. The layer composition is cupped.
ENEPIG
Electroless nickel plating, electroless palladium plating and substituted gold plating on copper, electroless nickel Electroless palladium immersion gold abbreviation. The layer configuration is Cu-Ni-Pd-Au
Electrolytic plating
A method for electrochemically precipitating a metal on a metal or non-metallic surface.
Electroless plating
A method of plating by chemical reaction without using an external power supply.
Substitution plating, reduction plating
Classification of electroless plating methods. It is broadly classified into a substitution method that uses a difference in the ionization tendency of metals and a reduction method that uses a reducing agent.
Soft gold plating, hard gold plating
Gold plating with a high purity (99.9% or more) is called soft gold plating, and hard gold plating is made by adding alloy components to reduce purity (99.9% or less) and increase hardness.
Bump plating
A plating method in which small metal protrusions (bumps) are formed on the electrodes of semiconductors. Bump formation allows the electrode and the substrate to be directly joined wirelessly, making it possible to reduce the size of electronic components.
Viafill plating
When the number of layers in a circuit reaches two or more, it is necessary to electrically connect the conductor layers. The hole used for the connection is called a beer hole, and it is a plating method that fills the beer hole.
PPF
LeadFrame plating method. It is an abbreviation for pre-plated LeadFrame, and in the case of pudo-plating, it is generally described as Pd-PPF (Palladium Pre-Plated LeadFrame).
Plating process
Pre-treatment
In the plating process, various processes before the substrate is placed in the plating bath. This applies to degreasing, etching, and acid cleaning processes.
Post-treatment
In the plating process, various processes after the substrate is placed in the plating bath. This applies to plating processes, sealing treatments, etc.
Sealing
When the film becomes thinner due to gold saving, pinholes (microscopic pores) are formed. After plating, the anti-rust effect is enhanced by treatment with a sealing agent.
Defatting
An operation to remove and clean oily stains adhering to the substrate.
Etching
A method of chemically or electrochemically corroding a metallic or non-metallic surface. In the case of plating on a resin, the resin is immersed in a liquid containing an oxidizing agent, and surface roughening and chemical change are performed at the same time.
Plating-related terms
Micro switch
A small switch that opens and closes by a mechanism that switches instantaneously with a narrow distance between contacts. Since the contacts are switched instantaneously, the duration of the arc is short, and a large current can flow even in a small size.
Connector
A connection terminal for electrically connecting a number of electronic components or printed circuit boards.
Printed circuit board
A general term for a board formed by wiring circuits that mount electronic components such as capacitors.
Rigid board
A circuit board with an inflexible insulator substrate.
Flexible substrate
A substrate that is flexible, can be deformed repeatedly with a weak force, and maintains its electrical properties even when deformed. Compared to rigid substrates, it has superior workability, so complex shape processing is possible.
Leadframe
A thin sheet of metal used as the internal wiring of semiconductor packages, which serves as a bridge to external wiring, and is used in the majority of semiconductor packages.
Leadframe Package Transition Diagram
QFP
Abbreviation for Quad Flat Package. A surface-mount LeadFrame package with external terminals coming out from all four sides of the package.
QFN
Abbreviation for Quad Flat Non-Lead Package. A surface-mount LeadFrame package in which the external terminals in all four directions of the package are located on the back of the package.
BGA
A solder ball is arranged on the electrode of the package, and is used for connection with a printed wiring board. Abbreviation for Ball Grid Array.
CSP
Abbreviation for Chip Size Package. An ultra-small package that is about the same size as an IC chip. By using CSP, the board mounting area of the set can be greatly reduced.
PoP
Abbreviation for Package on Package. With the increasing demand for higher density and space-saving substrates with the spread of smaller, thinner electronic devices, PoP mounting has been applied as a technology to achieve space saving.
LGA
A substrate on which electrode pads such as copper are arranged on the bottom of the IC package to form terminals. Abbreviation for Land Grid Array.
FIWLP
Abbreviation for Fan In Wafer Level Package. A type of wafer-level package that uses a semiconductor process to create a rewired layer that connects a semiconductor chip and a printed wiring board. The package area and the semiconductor chip area are the same.
FOWLP
Abbreviation for Fan Out Wafer Level Package. A type of wafer-level package that uses a semiconductor process to create a rewired layer that connects a semiconductor chip and a printed wiring board. The package area is larger than the semiconductor chip area, and the terminal can be extended to the outside of the chip (fan out). It can also be used in applications where the number of terminals is large compared to the chip area.
Coreless PCB
A semiconductor package substrate that does not use a core material (copper-clad laminate).
TSV
The name is an acronym for Through-Silicon Via, which refers to a through-silicon electrode in a semiconductor.
SAP Substrate
SUP is an abbreviation for Semi Additive Process, a substrate in which resist is formed in advance on the non-circuit part and only the circuit part with a seed layer (palladium, etc.) is plated.
MSAP Substrate
Modified Semi Additive Process, which is said to be relatively easy to make fine wiring, with the difference that SAP requires the formation of a seed layer while MSAP forms a wiring by plating on an ultra-thin Cu foil.
Protecting Agent
A series of organic compounds that selectively adsorb to a specific metal and control the plating reaction and film properties by donating or attracting electrons.
Noble metal
In general, it refers to an expensive metal, but it is a metal that has a high electrode potential and is difficult to ionize, and therefore is not easily oxidized even when heated in air.
Base metal
It refers to a metal that has a greater ionization tendency than hydrogen and is easily oxidized when heated in air. Aluminum, iron, nickel, tin, etc. belong to this.
Dry Film Resist
A film-like resist material for forming circuits on copper. After temporarily protecting the surface during the plating process, it can be dissolved and removed with alkali.
Solder resist
A material that acts as an insulating film that protects the circuit pattern of copper wiring. Prevents solder from adhering to contacts other than those that make electrical connections and causing short circuits.
Wire bonding
A method of connecting an IC chip to a lead frame or printed circuit board with a metal wire (gold, aluminum, etc.).